Name Description Size
cairo-drm-bo.c 2885
cairo-drm-gallium-surface.c 22478
cairo-drm-i915-glyphs.c Each vertex is: 2 vertex coordinates 15792
cairo-drm-i915-private.h Each instruction is 3 dwords long, though most don't require all this space. Maximum of 123 instructions. Smaller maxes per insn type. 40571
cairo-drm-i915-shader.c XXX 81282
cairo-drm-i915-spans.c Operates in either immediate or retained mode. When given a clip region we record the sequence of vbo and then replay them for each clip rectangle, otherwise we simply emit the vbo straight into the command stream. 20043
cairo-drm-i915-surface.c XXX - Per thread context? Would it actually avoid many locks? 85000
cairo-drm-i965-glyphs.c throw error! 14723
cairo-drm-i965-private.h New regs for broadwater -- we need to split this file up sensibly somehow. 20848
cairo-drm-i965-shader.c Theory of shaders: 3 types of rectangular inputs: (a) standard composite: x,y, use source, mask matrices to compute texcoords (b) spans: x,y, alpha, use source matrix (c) glyphs: x,y, s,t, use source matrix 5 types of pixel shaders: (a) Solid colour (b) Linear gradient (via 1D texture, with precomputed tex) (c) Radial gradient (per-pixel s computation, 1D texture) (d) Spans (mask only): apply opacity (e) Texture (includes glyphs). Clip masks are limited to 2D textures only. 81753
cairo-drm-i965-spans.c Operates in either immediate or retained mode. When given a clip region we record the sequence of vbo and then replay them for each clip rectangle, otherwise we simply emit the vbo straight into the command stream. 10446
cairo-drm-i965-surface.c XXX FIXME: Use brw_PLN for [DevCTG-B+] 54403
cairo-drm-intel-brw-defines.h 3D state: 33974
cairo-drm-intel-brw-eu-emit.c Authors: Keith Whitwell <keith@tungstengraphics.com> 32965
cairo-drm-intel-brw-eu-util.c Authors: Keith Whitwell <keith@tungstengraphics.com> 3224
cairo-drm-intel-brw-eu.c Authors: Keith Whitwell <keith@tungstengraphics.com> 6972
cairo-drm-intel-brw-eu.h Authors: Keith Whitwell <keith@tungstengraphics.com> 26192
cairo-drm-intel-brw-structs.h Command packets: 30977
cairo-drm-intel-command-private.h 4-7 reserved 34891
cairo-drm-intel-debug.c current gtt offset 33114
cairo-drm-intel-ioctl-private.h CAIRO_DRM_INTEL_IOCTL_PRIVATE_H 1743
cairo-drm-intel-private.h cache surfaces up to 16 MiB 14260
cairo-drm-intel-surface.c Basic generic/stub surface for intel chipsets 13015
cairo-drm-intel.c 33739
cairo-drm-private.h dev_t 7131
cairo-drm-radeon-private.h CAIRO_DRM_RADEON_PRIVATE_H 3076
cairo-drm-radeon-surface.c workaround for broken <drm/radeon_drm.h> 12881
cairo-drm-radeon.c XXX temporary workaround 8011
cairo-drm-surface.c XXX invalid device! 10724
cairo-drm.c open(), close() 10717